About 3D Integrated Chips

The three-dimensional integrated circuit (3D-IC), which enables better integration density, faster on-chip communications and heterogenous integration, etc., has become an active topic of research. Despite its significant performance improvement over the conventional 2D circuits, 3D-IC also exhibits thermal issues due to its high power density caused by the stacked architecture. To fully exploit the benefit of 3D-ICs, future 3D-IC designs are expected to have significantly complex architectures and integration levels that would be associated with very high power dissipation and heat density. The conventional air cooling has already been proved insufficient for cooling stacked 3D-ICs since several microprocessors are stacked vertically, and the interlayer micro-channel liquid cooling provides a better option to address this problem. This chapter investigates several aspects of 3D-ICs with micro-channel heat sinks including their infrastructure, thermal and hydrodynamic modeling, current research achievements, design challenges, etc. We will also introduce a micro-channel based runtime thermal management approach which dynamically controls the 3D-IC temperature by controlling the fluid flow rate through micro-channels.

3D Integrated Chip: according to Wikipedia

 A three-dimensional integrated circuit (3D IC) is a MOS (metal-oxide semiconductor) integrated circuit (IC) manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or Cu-Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics.

3D integrated circuits can be classified by their level of interconnect hierarchy at the global (package), intermediate (bond pad) and local (transistor) level. In general, 3D integration is a broad term that includes such technologies as 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs); monolithic 3D ICs; 3D heterogeneous integration; and 3D systems integration.

International organizations such as the Jisso Technology Roadmap Committee (JIC) and the International Technology Roadmap for Semiconductors (ITRS) have worked to classify the various 3D integration technologies to further the establishment of standards and roadmaps of 3D integration. As of the 2010s, 3D ICs are widely used for NAND flash memory and in mobile devices.

Introduction

For the growth of semiconductor technology, three-dimensional integration of microsystems and subsystems has become essential. 3D integration needs a better knowledge of several interconnected systems overlapping each other. Vertical development greatly improves the functionality of the 3D IC technology and also reduces the complexity of the design exponentially. The integrated three-dimensional circuit (3D-IC) includes two or more layers of vertically stacked active electronic components. Stacking of conventional 2D chips helps improve the inter-chip bandwidth resulting in faster data exchange. This helps in significantly improving the performance of the overall system. 3D integration can also result in overall system energy savings due to reduced inter-chip communication overheads, increased integration densities leading to improved performance and functionality and co-integration of heterogeneous components. 3D integration is being touted as a significant approach to counter the slowing of Moore’s law.

The improvements in performance as well as heterogeneity which can enable co- integration of image sensors and processors can have a significant impact on future computer vision systems. 3D Integrated Circuits and Systems Design covers all 3D implementation elements, including 3D circuit and system design, new processes and simulation techniques, alternative 3D circuit and system communication schemes, application of new 3D device parts, and heat problems to reduce energy dissipation and improve 3D system efficiency. The figure 1.1 shown below indicates a stacked 3D-IC with four levels. Each active layer in the 3D-IC includes functional units like processor cores and memories, or heterogeneous devices like analog RF circuits, sensors, etc. Through-silicon-vias (TSVs) are inserted into the 3D-IC to produce signal / power / ground between distinct levels and enable communication between distinct layers of devices. 

What is a 3D IC?

3D ICs are integrated circuits (chips) that incorporate two or more layers of circuitry in a single package.  The layers are interconnected vertically as well as horizontally.  These multi-layer chips are usually created by manufacturing separate layers and then stacking and thinning them.  Vertical electrical connections – TSVs – pierce the underlying silicon substrates to connect the circuitry on the different layers.

The diagram below shows a single layer (a die) with TSVs, greatly simplified and not to scale:

Stacking can be done die-on-die, die-on-wafer, wafer-on-wafer, or in combination.  The thickness of the layers, the diameter of the TSVs, and the number and density of the TSVs are important factors in the performance of the finished 3D IC.  Below is a greatly magnified cross-section of an 8-layer stack (courtesy of Tezzaron Semiconductor):

Evolution of integrated circuit packaging

The device scaling also affects the interconnects at the packaging and system level. To connect the transistors with downsized scale to the outer world, more intermediate layers are required to facilitate the connections, more I/Os are required to distribute the power and signal lines, and more efficient yet complicated cooling technologies are required to reject the excessive heat from the IC and interconnects as well. The evolution of the electronic packages is illustrated in Figure 1.3.

Figure 1.3. Semiconductor packaging trend.

As shown in Figure 1.3, semiconductor packages are experiencing five major patterns during last five decades, which are lead-frame, organic substrate with solder balls (BGA), fan-in wafer-level chip-scale package, fan-out wafer-level packaging (FOWLP), and through-silicon via (TSV) technology for 2.5D/3D IC stacking, respectively.

DIP (dual in-line package) lead-frame packages dominated in 1950–70, followed by QFP, PLCC, and SOIC during 1980. TSSOP and TQFP were much finer pitched lead-frame packages in 1990. At the same time, BGA package appeared and gradually dominated in the market. After 2000, there were many packages showing off in the form of flip chip BGA, flip chip CSP, etc. Wafer-level packages (WLPs) were major package format due to low cost. Stacked CSP, fan-in WLPs, and fan-out WLPs are gradually burgeoning in the market. Especially fan-out WLP is becoming a mature technology after 2010.

In the trend of shifting from the conventional planar 2D chip packaging to the 3D packaging, advanced electronic packaging formats are to be conceptualized, designed, and manufactured to meet the various application scenarios. Among them, the 2.5D and 3D IC packaging and their hybrid combination are viewed as the most promising technologies. FOWLP provides a low-cost alternative for heterogeneous integration solution ahead of the 3D chip stacking. The initial package-on-package came after 2000 and gradually developed to a 3D package stack in different forms such as wire bonding and mix of flip chip.

Many efforts have been made on the development of 2.5D and 3D packages based on TSV technologies with accumulated experience and knowledge in the heterogeneous areas [3–5]. The general technology trend toward the 3D IC packaging has been shown in Fig. 1.1.3. A typical 3D IC package relies on the TSV technology as the enabling interconnects, driven by the memory stack, wide I/O, logic + memory, and field-programmable gate array (FPGA) package.

Classification of 3D Integrated Circuits

There are different manufacturing technologies for stacked 3D-ICs:

Wafer on Wafer: The electronic components are firstly built on two or more wafers. The wafers are then bounded together.

Die on Wafer: The electronic components are built on two different wafers. One wafer is diced and then stacked on the other wafer.

Die on Die: The electronic components are built on multiple dies; these dies are then bonded together

Despite the advantages, the 3D-IC also brings forth new challenges:

Design Challenges: The third dimension brings forth an additional control variable during the design of the electronic system. Conventional design tools are geared towards 2D technology. New EDA tools for 3D- ICs are necessary.

Thermal Issues: In 3D-ICs, since several layers of electronic components that dissipate power are stacked vertically, the power density is usually higher than 2D- ICs, leading to potential thermal issues. In addition, the oxide layer’s thermal conductivity (which is between silicon layers) is small and would therefore decrease the transfer of heat to the environment. This exacerbates the 3D-IC heat issues. New 3D-IC cooling solutions may be needed.

TSV Induced Overheads: 3D-ICs incorporate thousands of TSVs for interlayer communication as well as delivery of power/ground. These TSVs are causing additional overhead space. Due to the heat expansion mismatch between silicon and TSV filling material, TSVs also cause thermal-mechanical stress. The thermal stress causes potential reliability problems, such as cracking, and also timing violations since transistor delay will be influenced by thermal stress.

Cross talk between Layers: Coupling might occur between the top layer metal wires and the device on the active layer above it. Furthermore, in heterogeneous integration, the RF Signal might influence the logic and memory in other layers.

Overall, 3D Integration is a significant development which has a major impact on the design of future electronic systems

Design styles

Depending on partitioning granularity, different design styles can be distinguished. Gate-level integration faces multiple challenges and currently appears less practical than block-level integration.

Gate-level integration

This style assigns entire design blocks to separate dies. Design blocks subsume most of the netlist connectivity and are linked by a small number of global interconnects. Therefore, block-level integration promises to reduce TSV overhead. Sophisticated 3D systems combining heterogeneous dies require distinct manufacturing processes at different technology nodes for fast and low-power random logic, several memory types, analog and RF circuits, etc. Block-level integration, which allows separate and optimized manufacturing processes, thus appears crucial for 3D integration. Furthermore, this style might facilitate the transition from current 2D design towards 3D IC design. Basically, 3D-aware tools are only needed for partitioning and thermal analysis.[36] Separate dies will be designed using (adapted) 2D tools and 2D blocks. This is motivated by the broad availability of reliable IP blocks. It is more convenient to use available 2D IP blocks and to place the mandatory TSVs in the unoccupied space between blocks instead of redesigning IP blocks and embedding TSVs.[34] Design-for-testability structures are a key component of IP blocks and can therefore be used to facilitate testing for 3D ICs. Also, critical paths can be mostly embedded within 2D blocks, which limits the impact of TSV and inter-die variation on manufacturing yield. Finally, modern chip design often requires last-minute engineering changes. Restricting the impact of such changes to single dies is essential to limit cost. 

What is the difference between 3D Packaging, 2.5D interposers, and 3D ICs?

3D packaging refers to 3D integration schemes that rely on traditional methods of interconnect at the package level such as wire bonding and flip chip to achieve vertical stacks. Examples of 3D packages include package-on-package (PoP) where individual die are packaged, and the packages are stacked and interconnected with wire bonds or flip chip processes; and 3D wafer-level packaging (3D WLP) that uses redistribution layers (RDL) and bumping processes to form interconnects.

 

Figure 1.4 3D system consisting of silicon carrier with logic and memory chip on organic carrier

2.5D interposer is a configuration where dies are mounted side-by-side on a silicon, glass, or organic interposer using through silicon vias (TSVs) through the interposer. (When glass or organic laminate is used as the interposer substrate, the vias are called through glass vias (TGV) and through substrate via (TSV) respectively.) Communication between the dies takes place via circuitry fabricated on the interposer.

CMOS image sensors (CIS) have TSVs as backside vias to form interconnects, eliminate wire bonds, and allow for reduced form factor and higher-density interconnects. In all types of 3D packaging, chips in the package communicate using off-chip signaling, much as if they were mounted in separate package on a normal circuit board.

3D ICs can be divided into 3D Stacked ICs (3D-SICs), which refers to stacking IC chips and interconnecting them with TSVs; and true 3D ICs, which use fab processes to stack multiple device layers on a single chip, which may or may not use very-fine-pitch TSVs to form the interconnect.

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