About Topic In Short: | |
 | Who: Hanyang University researchers, led by M.S./Ph.D. student Sangwan Lee and Associate Professor Jaeduk Han, developed the system |
What: A highly linear, energy-efficient 108 Gb/s PAM-8 receiver frontend system implemented in 28nm CMOS for high-speed data communication | |
How: Through a multi-path architecture to enhance the linearity-power trade-off and a separated FFE path to compensate for channel loss without signal compression | |
Introduction: The Need for Speed and Efficiency
The accelerating demands of modern data infrastructure—including data centers, AI clusters, the metaverse, and supercomputers—require data transfer rates far exceeding 100 Gb/s. However, achieving high-speed data communication presents significant challenges: sending very fast PAM-8 signals often results in degraded signal quality, and conventional receivers consume excessive power while attempting to compensate for signal weakening over distance. To overcome these dual problems, researchers at Hanyang University have developed a novel solution: a highly linear, energy-efficient 108 Gb/s PAM-8 receiver frontend system implemented in 28nm CMOS.
{Hanyang University Researchers Propose 108 Gb/s PAM-8 Receiver Frontend System in
28nm CMOS}
The Technical Breakthrough
Effective processing of high-voltage, higher-order PAM-8 signals, which are essential for data rates above 100 Gb/s, necessitates an extremely linear receiver to maintain robust signal-to-noise ratios. The Hanyang University team, led by M.S./Ph.D. student Sangwan Lee and Associate Professor Jaeduk Han, achieved this breakthrough by designing a unique receiver that dramatically enhances the linearity-power trade-off. The resulting system is poised for immediate application as a core component in next-generation high-speed data communication infrastructure.
Key Architectural Innovations
The system’s exceptional performance is derived from two unique architectures tailored specifically for processing PAM-8 signals:
1. Multi-Path Architecture for Enhanced Linearity
The researchers dramatically improved the linearity-power trade-off by implementing a multi-path architecture. This architecture divides the signal path, allowing each separate path to manage a sub-range of the total dynamic range. This clever division reduces the number of required slicers or samplers, which, in turn, decreases the load on the final stage. The result is remarkable efficiency: the architecture successfully doubles the linearity with only a 20% increase in power.
2. Separated FFE Path for Loss Compensation
High-speed signals inevitably suffer from significant channel loss, making compensation via a Feed-Forward Equalizer (FFE) essential. Conventionally, the FFE must process large-voltage signals directly, often leading to signal compression. The Hanyang team solved this by designing a structure that completely separates the FFE path from the main signal path. This separated path calculates compensation values using only a small, attenuated signal, preventing compression and ensuring accurate channel loss compensation even when large input signals are handled. The system includes a two-tap FFE capability.
Performance Metrics
The novel highly linear receiver frontend system in 28nm CMOS exhibits impressive performance metrics:
- Data Rate: 108 Gb/s
- Input Range: 1.4 Vppd
- Total Power: 210.8 mW
- Energy Efficiency: 1.95 pJ/bit
Thus Speak Authors/Experts
The researchers emphasized the strategic design behind the new technology:
Mr. Sangwan Lee remarks: "In this research, we have maximized both power efficiency and signal processing capability through two unique architectures for processing 'PAM-8' signals, which are essential for next-generation high-speed communication."
Dr. Jaeduk Han concludes: "It will provide the backbone for complex AI services like real-time translation, advanced medical diagnostics, and autonomous driving systems to become faster and more universally available. Moreover, by providing the massive bandwidth required for immersive virtual and augmented reality experiences, it will help make a seamless virtual world a reality. Lastly, as global data demand continues to explode, our power-efficient approach will help reduce the energy footprint of data centers, contributing to sustainable technological growth."
Conclusion
This research is expected to accelerate the computational speed of supercomputers and dramatically increase communication speeds between servers in AI clusters, thereby facilitating the training of large-scale AI models and the processing of massive datasets. By providing the foundational technology for future 800G and 1.6T Ethernet networking equipment and contributing a power-efficient approach to sustainable data centers, the 108 Gb/s PAM-8 receiver is set to serve as the backbone for the next generation of applications over the next 5 to 10 years.
Hashtag/Keyword/Labels List
#PAM8Receiver #108Gbps #HighSpeedData #EnergyEfficiency #28nmCMOS #DataCenters #AIClusters #JaedukHan #SangwanLee #MultiPathArchitecture #FFE
References/Resources List
- https://www.electronicsforu.com/news/more-efficient-high-speed-data-receivers
- https://www.eurekalert.org/news-releases/1107182
- https://techxplore.com/news/2025-11-frontend-gbs-pam.html
- https://www.prnewswire.com/news-releases/hanyang-university-researchers-propose-108-gbs-pam-8-receiver-frontend-system-in-28nm-cmos-302624634.html
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